This invention relates to semiconductor devices in general and more specifically to semiconductor devices having multiple conductive layers.
Semiconductor devices, such as integrated circuits (ICs), are becoming increasingly complex. While the demand requires semiconductor manufacturers to continually improve the power and performance of their devices, demand also requires the devices to be made smaller. A common way to achieve a smaller device is to shrink the dimensions of existing devices. Another widely practiced method of keeping the device size to a minimum is achieved by building the devices in the vertical direction, rather than in the horizontal. This is apparent in today's double-level and even triple-level polysilicon and metallization processes. But with these multi-layered devices came problems with fabrication. Two of the problems which have arisen are 1) being able to isolate one conductive layer from another, and 2) providing a relatively planar surface on which subsequent layers will be deposited and patterned.
With regard to the isolation of conductive layers, insulating layers known as inter-level dielectrics or inter-level oxides were developed and implemented between the conductive layers. Common insulating materials used today include SiO.sub.2, Si.sub.3 N.sub.4, and doped oxides such as PSG (phospho-silicate glass) and BPSG (boron doped phospho-silicate glass). Deposition techniques of such materials include CVD (chemical vapor deposition) using SiH.sub.4 or TEOS (tetra-ethyl-ortho-silicate) source gases or using a spin-on-glass (SOG). The problem of planarization has been dealt with in a number of ways, including depositing a very thick insulating layer and etching the layer back until it is relatively planar, flowing a glass layer such that it becomes planar, and the use of SOG, which produces a planar surface at the time of deposition. The planarized layer can subsequently be masked and etched in order to make vias to the desired underlying conductor layer.
But again, demand continues to drive semiconductor manufacturers to reduce the dimensions of their devices further, such that new problems have developed with the aforementioned solutions. For example, since existing planarization methods provide blanket planarization (i.e. the entire surface of the device is planarized), areas which are to be etched to form contact holes or vias have insulation layers which are generally very thick, making it difficult to achieve the desired etch profiles in narrow regions. Alignment sequences also become more difficult as there is little room for alignment error. A misalignment might result in exposing a conductive layer, rather than isolating it. In addition to isolating conductive layers on top of one another, isolation between closely spaced conductive members which are adjacent to each other must also be guaranteed. This poses an even greater challenge since the thickness of the isolation layer needs to be minimized in order to satisfy the demands of smaller devices. Besides being difficult to etch in narrow regions, forming the actual contact becomes more difficult since it is harder to deposit conductive materials in regions with high aspect ratios.
Therefore, a need existed for an improved method of fabricating a semiconductor device, more specifically for a method for fabricating a multi-layer semiconductor device which would enable the isolation of side-by-side conductive members separated by sub-micron spaces and provide a self-aligned contact to a substrate. In addition, a need existed for such method to also provide planarization over selected areas of selected layers of the device.